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MC145745 motorola 1 product preview the MC145745 is a selectable modem chip compatible with itu v.21 (300 baud full duplex asynchronous) and v.23 mode 2 (1200 baud half duplex asynchronous). the builtin differential line driver has the capability of driving 0 dbm into a 600 w load with a 5 v single power supply. this device also includes a dtmf generator, dtmf receiver, callprogress tone detector, answer tone generator, and a receive timing control circuit. besides having a clock generator with a crystal oscillator connected to it, the device has a divider circuit to which input of a double frequency clock is possible from external sources, such as from a microcontroller unit (mcu). the serial control port (scp) permits the mcu to access internal registers for exercising the builtin features. a low consumption device, the MC145745 integrates various functions in a small package. this modem ic is best suited for telemeter and other applications of this type. ? conforms to itu v.21 and v.23 recommendations ? dtmf generator and receiver for all 16 standard digits ? capable of driving 0 dbm into a 600 w load (v cc = 5 v) ? automatic gain control (agc) amplifier for the dtmf receiver ? callprogress tone detector ? fourwire serial data interface (scp) ? programmable transmission and carrier detection levels ? fsk/dtmf analog loopback selftest function ? crystal oscillator (3.579545 mhz) and half divider circuit (7.159090 mhz) for external inputs ? operates in the voltage range of 3.3 5.5 v ? power down mode (i cc < 1 m a) this document contains information on a product under development. motorola reserves the right to change or discontinue this product without notice. order this document by MC145745/d
semiconductor technical data pin assignment fw suffix soic case 751m ordering information MC145745fw soic 28 1 5 4 3 2 1 10 9 8 7 6 11 12 13 14 20 21 22 23 24 25 26 19 27 28 18 17 16 15 gnd v ref cda tla test 1 rxd txd cd clko x1 x2 eclk pb0 gnd v cc rxa txa1 txa2 test 2 scpen scpclk scp rx scp tx reset pb3 pb2 pb1 v cc ? motorola, inc. 1996 rev 0 7/96
MC145745 motorola 2 block diagram rxa cda v ref txa2 txa1 clko pb0 pb3 cd txd rxd reset x1 x2 eclk tla v cc gnd scp tx scp rx scpen scpclk rx amp and agc control loopback path smoothing filter and tx gain control tone generator antialias and lowpass filter clock generator 1/2 dtmf receiver cpt detector fsk carrier detector fsk v.21 modem fsk v.23 modem 4 + timing control circuit
MC145745 motorola 3 pin descriptions pin location symbol type description 1, 14 gnd e ground e these are the ground pins of the digital and the analog circuits. the 0 v potential of the device is determined by the input voltage at these pins. 2 v ref e reference analog ground e this pin provides the analog ground voltage v cc /2, which is regulated internally. this pin should be decoupled to gnd with 0.1 m f and 100 m f capacitors. 3 cda e carrier detect level adjustment e the detection level for fsk/callprogress tone is determined according to the voltage at this pin. when v cc = 5 v and the carrier detection level bit (br3:b1) of the scp register is 0, or when v cc = 3.6 v and (br3:b1) is 1, the cda voltage is set to 1.25 v by the internal divider. this voltage sets the detection levels at on to off: 44 dbm (typ) and off to on: 47 dbm (typ). this high impedance pin should be decoupled to gnd with a 0.1 m f capacitor. the carrier detection level is proportional to the terminal voltage at this pin. an external voltage may be applied to this pin to adjust the carrier detect threshold. the following equations may be used to find the cda voltage requirements for a given threshold voltage. v cda = 256 x v on v cda = 362 x v off 4 tla e transmit level adjustment e this pin is used to adjust the transmit carrier level which is determined by the resistor (rtla) connected between this pin and gnd. the maximum level is obtained when this pin is shorted to gnd (rtla = 0). 5, 24 test 1, test 2 i/o test pins 1 and 2 e these test pins are for manufacturer's use only. these pins should be left open in normal operation. 6 rxd o receive data output e this pin is the receive data output. when the device is in the fsk mode, logic high on this pin indicates that the mark carrier frequency has been received from rxa, and the logic low indicates that the space carrier frequency has been received. 7 txd i transmit data input e this pin is the transmit data input. when the device is in the fsk mode, logic high on this pin generates the mark frequency at txa1 and txa2 output, and logic low generates the space frequency. 8 cd o carrier detect output e this pin outputs at low level if a valid fsk, dtmf, or cptd signal is received. if the pin is at high level, the receive data output pin (rxd) is internally clamped at high level to avoid erroneous output of received data caused by line noise. 9 clko o clock output e this pin provides a buffered 3.58 mhz clock output that can drive one cmos device such as the mc74hc04. 10 x1 o crystal oscillator circuit output e a 3.579545 mhz 0.1% crystal oscillator is tied to this pin with the other end connected to x2. 11 x2 i crystal oscillator circuit input e a 3.579545 mhz 0.1% crystal oscillator is tied to this pin with the other end connected to x1. x2 may be driven directly from an appropriate external clock source. 12 eclk i external clock input e eclk is the input of double frequency, 7.159090 mhz 0.1%, of the reference clock. this pin must be connected to gnd when not in use. 13 pb0 o dtmf receive data parallel output 0 (lsb) e pins 13, 16, 17, and 18 are the dtmf receive data parallel output occurring together with the cd (pin 8) data valid output. the outputs of these pins are valid as long as the cd pin is low. in power down modes 1 and 2, the dtmf receiver is disabled and these pins are in high impedance. 15, 28 v cc e positive power supply e these are the power supply pins for the digital and the analog circuits. these pins should be decoupled to gnd with 0.1 m f and 100 m f capacitors. 16, 17, 18 pb1, pb2, o dtmf receive data parallel outputs 1, 2, and 3 (msb) e these pins are the dtmf receiver data 16 , 17 , 18 pb1 , pb2 , pb3 o dtmf receive data parallel outputs 1 , 2 , and 3 (msb) e these pins are the dtmf receiver data parallel outputs see pin 13 for more details pb3 para ll e l ou t pu t s. s ee p i n 13 f or more d e t a il s. 19 reset i reset e a high to low trigger pulse applied to this pin sets all the registers in the default state. it should remain at high during normal operations. 20 scp tx o scp output transmit e refer to serial control port (scp interface) for additional information. 21 scp rx i scp receive input e refer to serial control port (scp interface) for additional information. 22 scpclk i scp clock e refer to serial control port (scp interface) for additional information. 23 scpen i scp enable e refer to serial control port (scp interface) for additional information.
MC145745 motorola 4 pin descriptions (continued) pin location description type symbol 25 txa2 o transmit buffer output 2 (inverting) e this pin is the inverting output of the line driver. when v cc = 5 v, + 7 dbm (typ), differential output voltage (v txa1 v txa2 ), can be obtained with a load of 1.2 k w between pins txa1 and txa2. in typical applications, the output level on the telephone line will be half of the differential output (refer to application circuit ). 26 txa1 o transmit buffer output 1 (noninverting) e this pin is the noninverting output of the line driver. refer to txa2. 27 rxa i receive signal input e this pin is the analog signal input which has 500 k w input resistance (typ). absolute maximum ratings rating symbol value unit dc supply voltage v cc 0.5 to + 7.0 v dc input voltage v in 0.5 to v cc + 0.5 v dc output voltage v out 0.5 to v cc + 0.5 v dc input current i in 20 ma dc output current i out 25 ma power dissipation p d 500 mw storage temperature range t stg 65 to + 150 c recommended operational conditions parameter symbol min typ max unit dc supply voltage v cc 3.3 5.0 5.5 v dc input voltage v in 0 e v cc v dc output voltage v out 0 e v cc v crystal oscillation frequency f osc e 3.579545 e mhz external input frequency (eclk) e 7.15909 e operating temperature range t a 30 25 + 85 c dc electrical characteristics (v cc = + 3.3 to + 5.5 v, t a = 30 to + 85 c) characteristic symbol conditions min typ max unit input voltage (txd, eclk, reset , scp r scpclk high level v ih 0.7 x v cc e e v ( scp rx, scpclk, scpen ) low level v il e e 1.1 output voltage (rxd cd clko high level v oh v in = v ih or v il , i out = 20 m a v cc 0.1 v cc 0.01 e (rxd, cd, clko, pb03, scp tx) low level v ol v in = v ih or v il i out = 20 m a i out = 2 ma e e 0.01 e 0.1 0.4 input leakage current (txd, eclk, reset , scp rx, scpclk, scpen ) i in v in = v cc or gnd e 1.0 10.0 m a quiescent supply current v cc = 5 v i cc fsk mode, rtla = 0 txa1 and txa2 open e 7 e ma dtmf receive mode, no input e 9 e v cc = 3.6 v i cc fsk mode, rtla = 0 txa1 and txa2 open e 6 e dtmf receive mode, no input e 8 e powerdown supply current i cc powerdown mode 1 e e 500 m a powerdown mode 2 e e 1.0 m a this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is advised that normal precautions be taken to avoid ap- plications of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range gnd (v in or v out ) v cc . reliability of operation is enhanced if unused logic inputs are tied to an appropriate logic volt- age level (e.g., either gnd or v cc ).
MC145745 motorola 5 ac electrical characteristics (v cc = + 3.6 v 0.3 v, t a = 30 to + 85 c) transmit carrier characteristics characteristic symbol conditions min typ max unit v.21 carrier frequency originate mode mark a1o f 1m oscillation frequency: 3 579545 mhz (x2) 974 980 986 hz originate mode space a0o f 1s 3.579545 mhz (x2) or 7.159090 mhz (eclk) 1174 1180 1186 v.21 carrier frequency answer mode mark a1o f 2m or 7 . 159090 mhz (eclk) 1644 1650 1656 answer mode space a0o f 2s 1844 1850 1856 v.23 carrier frequency mark a1o f 1m 1294 1300 1306 space a0o f 1s 2094 2100 2106 transmit carrier level v o transmit attenuator = 0 db rtla 0 r l 12k w e 4 e dbm secondary harmonic level v 2h rtla = 0, r l = 1.2 k w v txa1 v txa2 e 40 e db outofband level v oe v txa1 v txa2 refer to figure 1 dbm transmit attenuator characteristics characteristic symbol conditions min typ max unit attenuation range 0 e 15 db attenuator accuracy 1 5 db 6 9 db 10 15 db 0.5 1 1.7 e e e 0.5 1 1 db receiver characteristics (includes hybrid, demodulator, and carrier detector) characteristic symbol conditions min typ max unit input resistance r irx 50 500 e k w receive carrier amplitude v irx 48 e 12 dbm carrier detection threshold off to on v cdon cda = 1.25 v f i 1 0 khz e 44 e dbm threshold on to off v cdoff f in = 1.0 khz br3 (b1) = 1 e 47 e hysteresis (v cdon v cdoff ) h ys br3 (b1) = 1 2 e e db carrier detection timing off to on t cdon cd1 = 0, cd0 = 0, cd pin e 450 e ms cd1 = 0, cd0 = 1, cd pin e 15 e cd1 = 1, cd0 = 0, cd pin e 15 e cd1 = 1, cd0 = 1, cd pin e 75 e on to off t cdoff cd1 = 0, cd0 = 0, cd pin e 30 e cd1 = 0, cd0 = 1, cd pin e 30 e cd1 = 1, cd0 = 0, cd pin e 15 e cd1 = 1, cd0 = 1, cd pin e 10 e cptd characteristics characteristic symbol conditions min typ max unit bpf center frequency f c e 400 e hz bpf passband lower cutoff frequency f i 3 db e 330 e hz bpf passband upper cutoff frequency f h 3 db e 470 e hz cpt detection level vtd on v tdon cda = 1.25 v f i 400 hz e 44 e dbm vtd off v tdoff f in = 400 hz br3 (b1) = 1 e 47 e cpt detection timing ttd on t tdon br3 (b1) = 1 e 10 e ms ttd off t tdoff e 25 e
MC145745 motorola 6 dtmf transmit characteristics characteristic symbol conditions min typ max unit tone output level low group v fl transmit attenuator = 0 db rtla 0 w e 0 e dbm high group v fh rtla = 0 w f osc = 3.579545 mhz e 1 e dbm high group preemphasis p e f osc = 3 . 579545 mhz single tone mode r l =12k w 0 e 3 db dtmf distortion dist r l = 1 . 2 k w v txa1 v txa2 e 5 e % dtmf frequency deviation d f v v txa1 v txa2 1 e 1 % outofband level v oe refer to figure 1 db setup time t osc e 4 e ms dtmf receiver characteristics characteristic symbol conditions min typ max unit input resistance 50 500 e k w detection signal level (each tone) br3 = (0, 0, 1, 0) 48 e 0 dbm twist (high/low group) 10 e 10 db frequency detection band width (figure 3) 1.5% + 2 hz 1.5% 2hz e e e e frequency nondetection band width (figure 3) e e 3.5% dtmf detection timing (figure 2) off to on delay tdv on cd1 = 0 , cd0 = 0 e 30 e ms (figure 2) delay cd1 = 0 , cd0 = 1 e 35 e cd1 = 1 , cd0 = 0 e 45 e on to off delay tdv off cd1 = 0 , cd0 = 0 e 25 e delay cd1 = 0 , cd0 = 1 e 35 e cd1 = 1 , cd0 = 0 e 25 e demodulator characteristics characteristic symbol conditions min typ max unit v.21 bit bias receive level = 24 dbm s/n = 4 db e 5 e % v.23 bit bias receive level = 24 dbm s/n = 14 db e 10 e % v.21 bit error rate receive level = 24 dbm s/n = 4 db 511bit pattern e 0.00001 e v.23 bit error rate receive level = 24 dbm s/n = 14 db 511bit pattern e 0.00001 e
MC145745 motorola 7 figure 1. outofband level 55 15 db/oct. f (hz) 256 k 16 k 4 k 3.4 k 0 0 25 transmit carrier level (dbr) figure 2. fsk, dtmf, and cpt carrier detection timing v on v off rxa cd t off t on figure 3. dtmf frequency detection bandwidth nodetect detect minimum width nodetect 3.5% 1.5% 2 hz + 1.5% + 2 hz + 3.5% f o
MC145745 motorola 8 scp timing characteristics ref. no. characteristic min max unit 1 scpen active before rising edge of scpclk 50 e ns 2 scpclk rising edge before scpen active 50 e ns 3 scp rx setup time before scpclk rising edge 35 e ns 4 scp rx hold time after scpclk rising edge 20 e ns 5 scpclk period 250 e ns 6 scpclk pulse width (low) 50 e ns 7 scpclk pulse width (high) 50 e ns 8 scp tx active delay time 0 50 ns 9 scpclk falling edge to scp tx high impedance e 30 ns 10 scpen inactive before scpclk rising edge 50 e ns 11 scpclk rising edge before scpen inactive 50 e ns 12 scpclk falling edge to scp tx valid data 0 50 ns figure 4. serial control port timing scp rx r/w a2 a1 a0 d3 d2 d1 d0 123456789 2 1 3 4 5 7 6 11 d3 d2 d1 d0 scp tx 9 12 8 10 scpen scpclk
MC145745 motorola 9 device description the MC145745 is a selectable modem chip compatible with v.21 (300 baud full duplex asynchronous) and v.23 mode 2 (1200 baud half duplex asynchronous). this device includes a dtmf generator, dtmf receiver, callprogress tone detector, answer tone generator, and a receive timing control circuit. the builtin differential line driver has the capability of driving 0 dbm into a 600 w load with a 5.0 v single power supply. the MC145745 also includes a serial control port (scp) that permits an mcu to exercise the built in features. the MC145745 provides an scp interface to access an in- ternal byte register which controls the device operations; such as function mode, carrier detect timing, transmit/receive gain, and transmit tones. the transmit and receive amplifiers' gain is programmable by scp register setting (br4). the tla pin is also available to adjust the transmit level that is determined by the resistor (rtla) value connected between the pin and gnd. the dtmf receiver amplifier includes a builtin agc amplifier which automatically adjusts the input amplifier gain corre- sponding to the amplitude of the dtmf tone input signal. the agc dynamic range can be selected in four options. the highest received sensitivity obtained is approximately 50 dbm when the dynamic range of the agc amplifier is maximized. the tone generator, which can generate 16 dtmf tones, is used at the terminal for transmission of the call and control tones. in addition, a single tone can be generated for tests and other uses. power down is amenable to software control by setting the byte register br2. while the device is in the power down state, scp still operates independently. there are two power down options available: power down 1 (the system clock operates alone) and power down 2 (the system clock stops). the clock generator constitutes an oscillation circuit with a 3.58 mhz crystal connected between the x1 and x2 pins. this device also has a 7.15909 mhz external clock input (eclk), which has a clock divider circuit for providing a 3.58 mhz clock to the internal circuits. if the eclk pin is used, the x2 pin should be held low. if the oscillation circuit (x1 and x2) is used, the eclk pin should be held low. this device also has a clock buffer output (clko), which can be used for providing a 3.58 mhz clock to the external device. table 1 shows the clock input and output relations in the dif- ferent modes. table 1. clock selection truth table fimd input output function mode eclk (pin 12) x2 (pin 11) clko (pin 9) pd1 0 fxtal fxtal power down 1 fext 0 fext/2 pd2 0 x 0 power down 2 fext 0 0 oh m d 0 fxtal fxtal other mode fext 0 fext/2 serial control port (scp interface) the MC145745 is equipped with an scp. the scp is a fullduplex fourwire interface with control and status in- formation passed to and from the internal register. the scp is compatible with the serial peripheral interface (spi) of single chip mcus used in other standard motorola devices. the scp consists of scp tx, scp rx, scpclk, and scpen for transmitting control data, status data, and dtmf receive data between the mcu and the MC145745. the scpclk determines the transmission and reception data rates, and the scpen governs when the data transaction is to take place. the operation/configuration of the MC145745 is pro- grammed by setting the state of the internal register bit. the control, status, and data information resides in 4bit wide registers which are accessed via the 8bit scp bus transac- tion. the first four bits of the 8bit bus transaction are the read/ write direction and the register address. the next four bits are the data written to or read from the internal registers. the scp interface is independent of the 3.58 mhz master clock. it runs by using scpclk as the synchronizing signal. scp transaction the scp interface includes both read and write capabili- ties, which together comprise the scp transaction. these scp transaction functionalities are described below. scp read the scp read action transaction is shown in figure 5. dur- ing the scp read action, the scpen pin must be in the low position. after scpen high goes low, then at the first four scpclk rising edges, read/write (r/w ) bit and three ad- dress bits (a0 a2) are shifted into the intermediate buffer register. if the read action is to be performed, the r/w bit must be at 1. and then, at the following four scpclk falling edges, the 4bit chosen register data is shifted out on scp tx. scpen must be restored to high after this trans- action, before another falling edge of scpclk is en- countered. while scp tx is in output mode, scp rx is disregarded. also, whenever scp tx is not transmitting data, a high impedance condition is maintained. scp write the scp write action transaction is shown in figure 6. during the scp write action, the scpen pin must be in the low position. after scpen high goes low, then at the first four scpclk rising edges, r/w and three address bits (a0 a2) are shifted into the intermediate buffer register. if the write action is to be performed, the r/w bit must be at 0. and then, at the following four scpclk rising edges, the 4bit data is shifted in from scp rx and written into the chosen register. during the write operation, scp tx is in high impedance. if the chosen register and/or the chosen bit are aread only,o the write action to it has no effect.
MC145745 motorola 10 ????? ????? ????? ????? figure 5. serial control port read operation scpclk scpen ???? ???? don't care ???? ???? a2 a1 a0 r/w don't care high impedance d3 d2 d1 d0 scp rx scp tx ????? ????? ????? ????? figure 6. serial control port write operation scpclk scpen ???? ???? don't care ???? ???? a2 a1 a0 r/w don't care high impedance d3 d2 d1 d0 scp rx scp tx description of the scp terminal the scp bus is made up of the following four pins. scp tx (pin 20) the scp tx pin outputs the control, status, and data in- formation from the 4bit wide register. during the read action transaction, a r/w bit and the three address bits are shifted in from scp rx at four scpclk rising edges, subsequent to scpen going low. after this, if a read operation is selected, scp tx comes out of the high impedance state at the first falling edge of scpclk, and outputs the first bit (msb) of the chosen register. the remaining three bits of the chosen reg- ister are shifted out from scp tx at the following three scpclk falling edges. after the last bit (lsb) is shifted out, scpen must return to high. then scp tx returns to the high impedance condition. scp rx (pin 21) the scp rx pin is used to input control and data informa- tion into the 4bit wide register. data is shifted in from scp rx at scpclk rising edge, while scpen is low. the first bit is the r/w bit (1 = read, 0 = write), and the next three bits address one of seven byteregisters. the address bits are shifted in msb first. if the write action is chosen, the 4bit data is shifted in from scp rx at the next four scpclk rising edges. if the read action is chosen, 4bit data in the selected register is shifted out on scp tx. scp rx is ignored while scpen is high. scpclk (pin 22) the scpclk pin is an input of standard clock for hand- shaking between scp and mcu. after scpen comes low and the scp transaction occurs, data is shifted from scp rx into the device at the rising edge of scpclk, and is shifted out on scp tx at the falling edge of scpclk. when scpen is high, scpclk is ignored (i.e., it may be continuous or it can operate in the burst mode). scpen (pin 23) when the scpen pin is held low, the scp transaction is enabled and control, status, and data information is trans- ferred. if scpen is returned to high, the scp action in prog- ress is aborted, and the scp tx pin enters a high impedance condition.
MC145745 motorola 11 scp register map the MC145745 register map is shown in table 2. seven of the 4bit wide byte registers (br) are provided in the register block. according to these published specifications, br signi- fies each register and the address of scp data. r/w is the read/write register, and ro is read only. if there is a high to low pulse on the reset pin or the power supply turns off, this register returns to the default state. the default condition that occurs after a power reset is as follows. br0 v.23 receive, transmit enable br1 dtmf cdon = 30 ms, dtmf cdoff = 25 ms fsk cdon = 450 ms, fsk cdoff = 30 ms br2 fsk mode br3 agc range = maximum, carrier detect level: high br4 transmission gain = maximum br5 dtmf transmission: 941 hz + 1633 hz br6 dtmf reception: unknown table 2. scp register map register b3 (bit 3: msb) b2 (bit 2) b1 (bit1) b0 (bit 0: lsb) br0 (r/w ) modem choice fsk channel transmission enable 0 v.23 v.21: answer v.23: receive enable 1 v.21 v.21: originate v.23: transmit disable br1 (r/w ) fsk cdt2 fsk cdt1 dtmf cdt2 dtmf cdt1 t cdon b3=0, b2=0 : 450 ms b3=0, b2=1 : 15 ms b3=1, b2=0 : 15 ms b3=1, b2=1 : 75 ms t cdoff b3=0, b2=0 : 30 ms b3=0, b2=1 : 30 ms b3=1, b2=0 : 15 ms b3=1, b2=1 : 10 ms t cdon b1=0, b0=0 : 30 ms b1=0, b0=1 : 35 ms b1=1, b0=0 : 45 ms t cdoff b1=0, b0=0 : 25 ms b1=0, b0=1 : 35 ms b1=1, b0=0 : 25 ms br2 (r/w ) (see table 3) function mode 4 function mode 3 function mode 2 function mode 1 br3 (r/w ) agc range 2 agc range 1 carrier detect level 1 test 0 b3=0, b2=0 : 5 to + 20 db b3=0, b2=1 : 5 to + 15 db high level (set when v cc = 5 v) normal 1 b3=1, b2=0 : 5 to + 10 db b3=1, b2=1 : 5 to + 5 db low level (set when v cc = 3.6 v) test mode br4 (r/w ) (see table 4) transmission gain 4 transmission gain 3 transmission gain 2 transmission gain 1 br5 (r/w ) (see table 5) tone transmission 4 tone transmission 3 tone transmission 2 tone transmission 1 br6 (ro) (see table 5) dtmf reception 4 dtmf reception 3 dtmf reception 2 dtmf reception 1 notes: 1. br0 (b0) is a nonworking bit. 2. dtmf loopback data is entered into br5 and output from the parallel port.
MC145745 motorola 12 table 3. function mode setup register b3 b2 b1 b0 comments fsk mode 0 0 0 0 the device works as one of two fsk modes, v.21/v.23. fsk loopback 0 0 0 1 the fsk modulator is internally connected to the fsk demodulator. cpt detect mode 0 0 1 0 the device works as the 400 hz tone detector. answer tone transmission mode 0 0 1 1 the device works as the 2100 hz answer tone generator. dtmf transmission mode 0 1 0 0 the device works as the dtmf generator. the receiver is disabled. single tone transmission mode 0 1 0 1 the device outputs one of the eight tones used for dtmf. power down 1 0 1 1 0 whole circuits except for the scp and the oscillator circuit are disabled. power down 2 0 1 1 1 whole circuits except for the scp are disabled. dtmf reception mode 1 0 0 0 the device works as the dtmf receiver. the received dtmf tone is demodulated to the 4bit code, then output from the scp interface and/or the parallel port. dtmf loopback 1 0 0 1 the dtmf generator is internally connected to the dtmf receiver, then the dtmf code written in br5 is loopbacked to the parallel port (pb0 pb3). table 4. transmission attenuator range transmission attenuator range b3 b2 b1 b0 0 db 0 0 0 0 1 db 0 0 0 1 2 db 0 0 1 0 3 db 0 0 1 1 4 db 0 1 0 0 5 db 0 1 0 1 6 db 0 1 1 0 7 db 0 1 1 1 8 db 1 0 0 0 9 db 1 0 0 1 10 db 1 0 1 0 11 db 1 0 1 1 12 db 1 1 0 0 13 db 1 1 0 1 14 db 1 1 1 0 15 db 1 1 1 1
MC145745 motorola 13 table 5. tone generator/receiver data k tone generator br5/br6 setting or data output k tone receiver si l t b3 b2 b1 b0 key input low group frequency (hz) high group frequency (hz) single tone (hz) b3 b2 b1 b0 d 941 1633 941 0 0 0 0 1 697 1209 697 0 0 0 1 2 697 1336 697 0 0 1 0 3 697 1477 697 0 0 1 1 4 770 1209 770 0 1 0 0 5 770 1336 770 0 1 0 1 6 770 1477 770 0 1 1 0 7 852 1209 852 0 1 1 1 8 852 1336 1336 1 0 0 0 9 852 1477 1477 1 0 0 1 0 941 1336 1336 1 0 1 0 * 941 1209 1209 1 0 1 1 # 941 1477 1477 1 1 0 0 a 697 1633 1633 1 1 0 1 b 770 1633 1633 1 1 1 0 c 852 1633 1633 1 1 1 1
MC145745 motorola 14 clko x1 x2 txa1 txa2 cda tla test1 test2 v ref 0.1 m f v cc +5 v 600 : 600 10 w 600 w tip ring gnd line protection circuit reference analog ground system ground * * figure 7. application circuit MC145745 rxa reset 100 m f txd rxd cd scpclk scp rx scp tx mcu i/o port scpen 0.1 m f 0.1 m f 100 m f +5 v eclk 3.579545 mhz pb0 pb3 4
MC145745 motorola 15 package dimensions fw suffix soic case 751m01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. maximum mold protrusion shall not exceed 0.15 (0.006) per side. 4. dimension d does not include dambar protrusion. dambar protrusion shall not cause the lead width to exceed 0.65 (0.026). dim a min max min max inches 17.80 18.03 0.701 0.710 millimeters b 7.40 7.62 0.291 0.300 c 2.65 0.104 c1 2.25 2.45 0.090 0.096 d 0.35 0.51 0.014 0.020 e 10.00 10.60 0.394 0.414 f 0.40 0.70 0.016 0.028 g 1.27 bsc 0.050 bsc j 0.10 0.25 0.004 0.010 l 0.635 bsc 0.025 bsc q 8 8 v 0.25 0.75 0.010 0.030 w 0.05 0.20 0.002 0.008 x 1.40 ref 0.055 ref c l y 0.25 (0.010) m tz ss a b 114 15 28 28x d z 0.18 (0.007) m ty ss 0.18 (0.007) m t 0.10 (0.004) t e view ab v x 45 5 c w seating plane q j f z c1 w ref view ab y z t g l 4x 24x
MC145745 motorola 16 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 20912; phoenix, arizona 85036. 18004412447 or 6023035454 3142 tatsumi kotoku, tokyo 135, japan. 81335218315 mfax : rmfax0@email.sps.mot.com touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok r oad, tai po, n.t., hong kong. 85226629298 MC145745/d ?

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